What I work on
I focus on designing microarchitectures, integrating subsystems, ensuring timing closure, and verifying AI accelerators. My work spans accross performance-optimized designs, precision-aware arithmetic, and verification methodologies.
Skills
Languages
EDA Tools
DV Concepts
Architecture
Workflow
Experience
- Architected a 55-module FPGA SoC accelerator (Winograd PE array, hierarchical NoC, DMA engine, multi-bank memory, control FSMs) with end-to-end RTL design and subsystem integration.
- Designed distributed SystemVerilog RTL and FSM control for compute scheduling and memory sequencing, integrating vendor DDR4 EMIF and BRAM IP over AXI.
- Achieved 250 MHz timing closure on Intel Arria-10 via synthesis, STA, pipelining, retiming, and register balancing.
- Reduced ASIC power 4–7% with variable-precision arithmetic units minimizing switching activity under Design Compiler.
- Built self-checking testbenches with golden-reference models and Python/Tcl regression across 15+ configs, cutting debug turnaround 60%.
- Evaluated spatial, depth-wise, and capacity-based tiling strategies for PE-array mapping, balancing compute utilization against on-chip memory and DSP constraints.
- Developing an embedded edge-AI FPGA platform for Weigh-In-Motion calibration, fusing computer vision and axle-sensor streams for real-time vehicle weight estimation.
- Building automated multimodal data-acquisition and validation pipelines across 10,000+ test passages, profiling latency and accuracy pre-deployment.
- Researched fault-tolerant system architectures for deep neural networks, targeting resilience under hardware-induced errors.
- Implemented TinyML inference pipelines for edge deployment, optimizing for latency under constrained resources.
- Programmed FPGAs in Verilog for hardware customization, tuning performance and efficiency.
- Shadowed the FPGA/ASIC design team on-site to study industry RTL flows, verification methodology, and chip design practices outside coursework.
- Developed a LoRaWAN-based monitoring system with cloud integration, implementing embedded C firmware for sensor data acquisition on ESP32 nodes over SPI/I2C.
- Built a Raspberry Pi–based gateway and secured the communication stack with cybersecurity protocols for a final-year IoT research project.
Projects
Winograd CNN Accelerator
RTL accelerator on ZCU102 hitting 5.3 TOPS on VGG16 via streamed dataflow optimization and simulation-based functional verification. Extended into an overlap-aware streaming architecture, ready for journal submission.
Power-Efficient POSIT Multiplier
Timing-aware Verilog RTL for decode, multiply, and recode pipeline stages; synthesized in Synopsys Design Compiler, validating 4–7% power reduction via switching-activity analysis.
Depthwise Separable CNN Accelerator
Parallel RTL architecture for MobileNet-class models achieving ~20× speedup through dataflow parallelism.
DFT for Systolic Arrays
Scan chains and BIST for systolic PE arrays, improving fault coverage and enabling structured post-silicon validation.
Fault Tolerance Enhancement for DNNs
Investigated fault-tolerant architectures for deep neural network accelerators under hardware-induced error models.
Dynamic 32×64 LED Matrix Display
Xilinx FPGA design driving a high-resolution LED matrix at 30 fps, with UART-based visual data ingestion and clock/data synchronization.
Education
M.Sc. Electrical Engineering
B.Sc. Computer Systems Engineering
Soft Skills
Leadership & Mentorship
Led a project team and mentored peers (7-member team, K2X); mentored students as a Teaching Assistant.
Communication & Presentation
Presented extensively in graduate courses; liaised with international clients and stakeholders.
Teaching & Community
TA for Probability & Statistics (UofS, 2026) and high-school math; Microsoft Learn Student Ambassador; IEEE Student Member.
Volunteering
Student Wellness Center, UofS — event logistics; Media Team, University Computer Society.
Customer Service
POS operations, cash handling, and client-facing service, APS Stationary.
Cross-Functional Collaboration
3+ years of general software engineering experience (K2X, Dcube, Auxcube, The Solutioners) coordinating with product, client, and research teams.
Let's build something.
Open to RTL / FPGA / verification roles and research collaborations. Reach out — I reply fast.